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Reducing the Branch Penalty of Mispredicted Short Forward Branches
| Content Provider | Semantic Scholar |
|---|---|
| Author | Tyson, Gary S. Farrens, Matthew K. Rich, Kevin D. Pleszkun, Andrew R. |
| Copyright Year | 1999 |
| Abstract | Many new high-performance microprocessor designs are incorporating much shorter clocks, deeper pipelines and increased support for multiple instruction issue. The complexities of superscalar issue, however, often require the addition of extra pipeline stages before the execution stage. Having multi-cycle decode and issue stages intensifies the problem of pipeline bubbles due to changes in control flow while branch prediction can keep the pipeline full of instructions when a branch outcome is correctly predicted, there can be a substantial penalty for flushing instructions and then restoring the proper sequence of instructions on a misprediction. In this paper, we show that a large percentage of cycles lost due to incorrectly predicted branches are caused by short forward branches, we examine the inefficiencies of pipeline flushing found in current prediction implementations, and we propose some new techniques which can reduce the branch penalty for a significant portion of mispredicted branches. Our simulation results indicate that a 5-15% reduction in the branch penalty can be achieved currently, and savings of 19-30% are possible in the future (as basic block sizes increase). |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://american.cs.ucdavis.edu/publications/cse-95-7.ps |
| Alternate Webpage(s) | http://www.cs.ucdavis.edu/research/tech-reports/1995/CSE-95-7.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
