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A 0 . 25m , 600-MHz , 1 . 5V , Fully Depleted SOI CMOS 64-Bit Microprocessor
| Content Provider | Semantic Scholar |
|---|---|
| Author | Park, Sung Bae Kim, Young Wug Ko, Young Gun Kim, Kwang Il Kwon, Il Kang, Hee-Sung Suh, Kwang Pyuk |
| Copyright Year | 1999 |
| Abstract | A 0.25m, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in highspeed dynamic circuits without body contact. C–V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://isac-cpu.com/_files/200000030-9392d95f14/JSSC_Invited_1999.pdf |
| Alternate Webpage(s) | http://vlsi.yonsei.ac.kr/seminar/34ssc11-spark.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
