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A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS
| Content Provider | Semantic Scholar |
|---|---|
| Author | Chung, Hayun Rylyakov, Alexander V. Deniz, Zeynep Toprak Bulzacchelli, John F. Wei, Gu-Yeon Friedman, Daniel J. |
| Copyright Year | 2009 |
| Abstract | A 7.5-GS/s 4.5-bit analog-to-digital converter (ADC) in 65nm CMOS is presented. A two-stage track-and-hold (TAH) with clock duty cycle control reduces bandwidth requirements on the slow TAH output to enable high sampling rates with low power consumption. The 7.5-GS/s flash ADC consumes 52-mW and occupies 0.01-mm2. Clock duty cycle control improves ENOB from 3.5 to 3.8 with an input sinusoid at the Nyquist frequency. |
| Starting Page | 268 |
| Ending Page | 269 |
| Page Count | 2 |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://researcher.watson.ibm.com/researcher/files/us-sasha/7.5Gbps_ADC_Hayun_VLSI2009_26_2_4.pdf |
| Journal | 2009 Symposium on VLSI Circuits |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |