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A SYSTEM-ON-CHIP RADIATION HARDENED MICROCONTROLLER ASIC WITH EMBEDDED SPACEWIRE ROUTER Session : SpaceWire Components Long Paper
| Content Provider | Semantic Scholar |
|---|---|
| Author | Berger, Richard Burcin, L. Hutcheson, David P. Koehler, Jennifer W. Lassa, Marla Milliser, Myrna Moser, David Stanley, Dan Zeger, Randy Blalock, Ben |
| Copyright Year | 2007 |
| Abstract | A mixed-signal radiation hardened computer ASIC that includes a four port SpaceWire router is currently in development. Based on the RAD6000 microprocessor currently flying on numerous space missions and commanding the Mars Exploration Rovers, this massively integrated system-on-chip is capable of performing flight computer and instrument controller functions and can reuse existing RAD6000 software and test infrastructure. The ASIC will be manufactured in a 150nm radiation hardened CMOS technology. Initiated in 2005 as a NASA technology project, development has continued with funding from the Air Force Research Laboratory’s Space Vehicles Directorate, Kirtland Air Force Base, N.M.. The ASIC incorporates an enhanced version of the reusable SpaceWire router core with four SpaceWire links and dual internal ports that was previously created for the BAE Systems SpaceWire ASIC. This newer version reduces both die area and power dissipation while improving link performance. The ASIC employs a flight-proven reusable core architecture with a common bus medium. In addition to the RAD6000 microprocessor and SpaceWire cores, the ASIC includes a pipelined 12-bit A/D converter with a programmable multiplexer, three channels of 12-bit D/A conversion, 192KB of on-chip SRAM, 32KB of chalcogenide-based C-RAM non-volatile memory, a 64-bit PCI interface, a 1553 interface, a DMA controller, and an external memory controller. A 2 smaller microcontroller core called the EMC has also been incorporated on the ASIC. It is supported by a compiler developed by BAE Systems and software supporting the SpaceWire transport layer has already been developed. This paper discusses the architecture and functions of the microcontroller ASIC, including the SpaceWire core implementation and features. Operational configurations matched to a variety of applications will also be shown. Approved for public domain release (VS07-0571) ©2007 BAE Systems All rights reserved INTRODUCTION TO THE RAD6000MC MICROCONTROLLER Based on the BAE Systems flight-proven RAD6000 microprocessor and integrating a wide variety of digital and analog interfaces and both SRAM and non-volatile memory, the RAD600MC is a true system-on-a-chip. It is being designed for a variety of applications that include both flight computer processing and instrument control. It supports both legacy buses such as MIL-STD-1553 and the rapidly growing SpaceWire serial bus through an integrated four-port router with dual internal interfaces. The RAD6000MC also supports up to 48 analog input channels, making it ideal for interface with spacecraft sensors and includes three channels of D/A conversion. Non-volatile memory is implemented with a new embedded C-RAM memory macro. Much of the RAD6000MC design is reused from ASICs already proven in hardware and/or currently in development, decreasing both the design cost and risk associated with the program. The ASIC will be manufactured in a radiation hardened 150nm CMOS technology. RAD6000 MICROPROCESSOR BACKGROUND AND CORE TRANSLATION Originally developed by IBM in 1990 as the first single chip implementation of the RISC System/6000 “Power” architecture [1] and the predecessor to the PowerPC line of microprocessors, the RAD6000 microprocessor [2] was created in 1995 in a 0.5 micron radiation hardened CMOS technology by modifying the circuitry for reliable spaceborne operation. This processor was quickly adopted and has been employed in many NASA missions as the flight computer, as well as the command processor in both generations of the Mars rovers. As shown in Figure 1, the RAD6000 central processor unit (CPU) includes both fixed point and floating point execution units in a superscalar RISC architecture executing up to three instructions per cycle. A two-way set associate unified 8 KB cache memory is also included. The existing microprocessor component is capable of operation at up to 33 MHz, with a throughput of 35 MIPS. The processor was originally developed using IBM’s proprietary design languages and design tools. Separate buses are provided for I/O and memory. The RAD6000 is supported by the VxWorks real time operating system from WindRiver and a Green Hills C Compiler. Diagnostics are supported using the RAD6000’s Common On-Chip Processor (COP) function. When ported to a 150nm CMOS technology, the RAD6000 decreases in size by almost six times, making it quite viable for use as an embedded processor core. However, there were several steps required to bring that to fruition. The first step was to translate the logic design into VHDL to create a model compatible with industrystandard simulation tools that would ease simulation with other cores. The translated model was validated both with functional simulations and simulations of the original design’s manufacturing test patterns. All existing Interfaces and the original Level Sensitive Scan Design (LSSD) latches were maintained in order to allow validation post-manufacturing using the current test patterns as well. The COP function was enhanced with the addition of a slave interface to the On Chip Bus [3] to complement the existing off-chip interface for connection to existing RAD6000 diagnostic tools. This change will allow access to the COP from the JTAG cores as an alternative diagnostic approach. Approved for public domain release (VS07-0571) ©2007 BAE Systems All rights reserved Unified 8KB Data / Instruction Cache Memory Interface Unit Pipeline Control Unit Input / Output Sequencer Unit Instruction Queue & Dispatch Fixed Point Execution Unit (FXU) Floating Point Execution Unit (FPU) Common On-Chip Processor (COP) Test Unit Memory Management Unit (MMU) Memory Bus w/ECC I/O Bus Data / Inst Addr Data Cntl Virtual Address Instructions Data Instruction Address D ta Aress Data Instructions COP Bus Controls to/from Other Units Branch Processor& Instruction Fetch |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.2007.spacewire-conference.org/proceedings/Papers/Components%202/berger.pdf |
| Alternate Webpage(s) | http://2007.spacewire-conference.org/proceedings/Presentations/Components%202/berger.pdf |
| Alternate Webpage(s) | http://www.2007.spacewire-conference.org/proceedings/Abstracts/Components%202/berger.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
