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Self-aligned Metal Double-gate P-channel Low-temperature Poly-Si TFTs Fabricated by DPSS CW Green Laser Lateral Crystallization
| Content Provider | Semantic Scholar |
|---|---|
| Author | Sato, Tadashi Hirose, Kenta Kitahara, Kuninori Hara, Akito |
| Copyright Year | 2009 |
| Abstract | Self-aligned top and bottom metal double-gate (DG) p-channel (p-ch) low-temperature (LT) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) were fabricated at 550°C. High-quality Si thin film, which was fabricated by diode-pumped solid-state (DPSS) continuous wave (CW) green laser lateral crystallization, was used as the channel layer. It was observed that the on-current of the TFTs was nearly double that of the top-gate (TG) p-ch LT poly-Si TFTs, and the S-value of the former was smaller than that of the latter. Introduction The multigate structure is considered to be the main candidate for realizing ideal Si transistors in the nano-CMOS era. This technique also leads to the improvement of the performance of poly-Si TFTs. High-quality poly-Si films are important for improving the performance of poly-Si TFTs. DPSS CW green laser crystallization is an excellent technique that can be used to fabricate large-grained poly-Si films, and one of the present authors (A.H.) has succeeded in realizing high-performance TG poly-Si TFTs on non-alkali glass substrates at 450 °C using this technique.[1–3] To fabricate LT poly-Si TFTs, particularly at temperatures below 600°C, the use of a metal gate is necessary. In the present study, we successfully fabricate self-aligned top and bottom metal DG p-ch LT poly-Si TFTs with large-grained poly-Si film that show good performance. Experiments Figure 1 shows a three-dimensional image of the TFTs during fabrication and an optical photograph of the actual devices after the completion of several key processes. Fused quartz glass was used in this experiment. After a bottom Mo gate was patterned (Figs. 1(a) and (a′)), a SiO2 layer and a a-Si layer were deposited by plasma-enhanced chemical vapor deposition (PECVD) at 325°C using SiH4 + N2O for the SiO2 deposition and SiH4 + H2 for the a-Si deposition. After dehydrogenation annealing at 500°C for 60 min in N2 gas, a-Si was crystallized by using a stable scanning DPSS CW green laser (ƛ = 532 nm, 2ω of Nd:YVO4) with a speed of 40 cm/s. The laser spot size in this experiment was set at 400 × 20 μm using two cylindrical lenses. The power instability of the DPSS CW green laser was less than 1%, which is less than the values in the case of XeCl excimer and Ar lasers. After Si-island formation by dry etching, the top SiO2 gate layer was deposited by PECVD (Figs. 1(b) and (b′)). Subsequently, the contact hole for connecting the top and bottom metal gates was formed by dry etching. After slight etching using a diluted HF solution to remove the oxidized layer on the surface of the bottom Mo gate, sputtered Mo was deposited. To form a self-aligned top Mo gate, back-surface exposure of the g-line was performed by using the bottom Mo gate as a mask. The film thickness of the top Mo gate was sufficiently small (30 nm) for the film to be transparent to g-line light. On the other hand, the bottom Mo gate was sufficiently thick (50 nm) for the film to act as a metal mask in the formation of the self-aligned top gate by back-surface exposure. After the wet etching of the sputtered top Mo metal, the self-aligned top Mo gate was fabricated (Figs. 1(c) and (c′)). After the removal of the SiO2 layer on the source and drain regions by dry etching, ion implantation of BF2 was performed with an acceleration energy of 20 keV and an ion dose of 3 × 10 cm. After annealing at 550°C for 6 h for activation, a SiO2 isolation layer and a Mo electrode were formed by PECVD and sputtering, respectively. Fig. 1. Three-dimensional images of poly-Si TFTs after the completion of key processes. The photographs to the right show the top view of an actual device after the processes. Figure 1(d′) shows a photograph of the top view of a metal DG p-ch LT poly-Si TFT. The active Si channel layer is undoped and is 100-nm thick. The top and bottom SiO2 gate layers are designed to be 50-nm thick. The maximum temperature in the poly-Si fabrication process was 550°C. Fused quartz glass was used in this experiment. It is well known that the DPSS CW green laser can be used for the crystallization of Si film on a non-alkali glass substrate;[1–3] thus, the technique developed in this experiment can easily be applied to non-alkali glass substrates. Results and discussions Figure 1(b′) shows an optical microscope image of a poly-Si island on the bottom Mo gate. The crystallized poly-Si film is composed of very large grains, which are generally parallel to one another and in the scan direction of the laser beam. The surface of the crystallized poly-Si film is very smooth, and the grain boundaries do not form ridges. Figure 2 shows Raman scattering spectra of the poly-Si film 30μm |
| File Format | PDF HTM / HTML |
| DOI | 10.7567/SSDM.2009.K-2-7 |
| Alternate Webpage(s) | https://confit.atlas.jp/guide/event-img/ssdm2009/K-2-7/public/pdf_archive?type=in |
| Alternate Webpage(s) | https://doi.org/10.7567/SSDM.2009.K-2-7 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
