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Implementation of error correcting methods to the asynchronous Delay Insensitive codes with reduced delay and area
| Content Provider | Semantic Scholar |
|---|---|
| Author | Reddy, Shilpa |
| Copyright Year | 2013 |
| Abstract | This Paper provides an approach for reducing delay and area in asynchronous communication. A new class of error correcting Delay Insensitive (ie., unordered) codes is introduced for global asynchronous communication.It simultaneously provides timing-robustness and fault tolerance for the codes.A systematic and weighted code is targeted. The proposed error correcting unordered (ECU) code, called zero-sum can provide 1-bit correction.The extensions to the zero-sum code are given.The zero_sum+ code provides 3-bit error detection,or it can provide 2-bit detection and 1-bit correction.The zero_sum* code support 2-bit correction,while still guaranteeing 2-bit detection under different strategies of weight assignments. Zero_sum* code provides 2-bit correction coverage (50 % to 70%) of all 2-bit errors. The proposed method reduces delay occurred, due to the transfer of corrupted bits in a packet on the channel by the removal of timer and also reduces the area with the proposed Completion Detector (CD). |
| File Format | PDF HTM / HTML |
| DOI | 10.9790/2834-0757885 |
| Alternate Webpage(s) | http://www.iosrjournals.org/iosr-jece/papers/Vol7-Issue5/O0757885.pdf?id=7633 |
| Alternate Webpage(s) | https://doi.org/10.9790/2834-0757885 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
