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Hide and seek in silicon – Performance analysis of Quad block Equisum Hardware Steganographic systems
| Content Provider | Semantic Scholar |
|---|---|
| Author | Rajagopalan, Sundararaman Janakiraman, Siva Upadhyay, Har Narayan Thenmozhi, K. |
| Copyright Year | 2012 |
| Abstract | Abstract Steganography has become a predominantly employed information security technique in this modern era. Although the software methods which work on spatial as well as transform domain steganography offer a lot of data hiding options, the steganographic system on hardware platform shows enormous potential by means of multiple advantages such as high speed embedding, specific hardware dependency etc.,. In this paper we have proposed image steganographic architecture which employs data embedding technique in square sized cover image blocks that are stored in internal/external memory of a processor and reconfigurable hardware. The traversal path for information hiding in cover image uses an equisum arrangement of the quad block locations which is used as a Look up Table in our approach. The K-bit message will be hidden in row by row and column by column according to the order suggested by the quad block. The proposed approach is implemented in Cyclone II EP2C20F484C7 FPGA as well as ARM7RISC Processor. The timing analysis, hardware consumption and error metrics after implementation in both platforms have been estimated. |
| Starting Page | 806 |
| Ending Page | 813 |
| Page Count | 8 |
| File Format | PDF HTM / HTML |
| DOI | 10.1016/j.proeng.2012.01.931 |
| Alternate Webpage(s) | https://core.ac.uk/download/pdf/81199739.pdf |
| Alternate Webpage(s) | https://doi.org/10.1016/j.proeng.2012.01.931 |
| Volume Number | 30 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
