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Register Promotion by Sparse Partial Redundancy Elimination ofLoads and StoresRaymond
| Content Provider | Semantic Scholar |
|---|---|
| Author | Chow, Fred Kennedy, Robert J. Liu, Shin-Ming Tu, Peng |
| Copyright Year | 1998 |
| Abstract | An algorithm for register promotion is presented based on the observation that the circumstances for promoting a memory location's value to register coincide with situations where the program exhibits partial redundancy between accesses to the memory location. The recent SSAPRE algorithm for eliminating partial redundancy using a sparse SSA representation forms the foundation for the present algorithm to eliminate redundancy among memory accesses, enabling us to achieve both computational and live range op-timality in our register promotion results. We discuss how to eeect speculative code motion in the SSAPRE framework. We present two diierent algorithms for performing speculative code motion: the conservative speculation algorithm used in the absence of proole data, and the the proole-driven speculation algorithm used when proole data are available. We deene the static single use (SSU) form and develop the dual of the SSAPRE algorithm, called SSUPRE, to perform the partial redundancy elimination of stores. We provide measurement data on the SPECint95 benchmark suite to demonstrate the eeectiveness of our register promotion approach in removing loads and stores. We also study the relative performance of the diierent speculative code motion strategies when applied to scalar loads and stores. 1 Introduction Register allocation is among the most important functions performed by an optimizing compiler. Prior to register allocation, it is necessary to identify the data items in the program that are candidates for register allocation. To represent register allocation candidates, compilers commonly use an unlimited number of pseudo-registers CAC + 81, TWL + 91]. Pseudo-registers are also called symbolic registers or virtual registers, to distinguish them from real or physical registers. Pseudo-registers have no alias, and the process of assigning them to real registers involves only renaming them. Thus, using pseudo-registers simpliies the register allocator's job. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://reality.sgi.com/dehnert_engr/papers/LCKLT98.ps |
| Alternate Webpage(s) | http://www.researchgate.net/profile/Robert_Kennedy12/publication/2467321_Register_Promotion_by_Sparse_Partial_Redundancy_Elimination_of_Loads_and_Stores/links/5449375c0cf2f63880810a90.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
