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Defying the Memory Bottleneck in Hardware Accelerated Collision Detection
| Content Provider | Semantic Scholar |
|---|---|
| Author | Raabe, Andreas Zavelberg, Frank |
| Copyright Year | 2008 |
| Abstract | A novel approach for hardware-accelerated high-speed collision detection is presented in this article. It focuses on dedicated hardware for collision detection queries and its interaction with the memory interface. A specialised tree-traversal algorithm is presented that exploits arbitrary memory interfaces optimally to minimise delay of collision queries. Along with this a novel caching technique is introduced that combines high-speed access to the bounding-volume hierarchy with minimal resource consumption. Simulation and synthesis results are presented that prove the conjunction of both techniques to enable real-time collision queries at rates required by force-feedback while fitting onto a standard field-programmable gate array. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://wscg.zcu.cz/wscg2008/Papers_2008/short/A29-full.pdf |
| Alternate Webpage(s) | http://www1.icsi.berkeley.edu/~raabe/publications/Raabe-Zavelberg-Memory-2008.pdf |
| Journal | WSCG 2008 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
