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Control of plasma-surface reactions for next generation semiconductor devices
| Content Provider | Semantic Scholar |
|---|---|
| Author | Tatsumi, Tetsuya |
| Copyright Year | 2011 |
| Abstract | According to “Moore’s law”, transistor size will be shrunk to below several tenth nanometers. In fabricating high performance ultra-large-scale integrated (ULSI) devices, it is necessary to suppress both the variation of the critical dimension (CD) of the gate electrode and the degradation of the Si substrate (dislocation of Si atoms in the Si – Si network) to within several atomic layers.[1-3] The length of gate electrodes (Lg) depends on the mask profile, including line width roughness (LWR), etch rate uniformity within a wafer and/or within a lot, and the pattern (space) width. The damage to the Si substrate occurs both during gate etching and the etching of sidewall dielectric materials (see Fig. 1). |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.ispc-conference.org/ispcproc/ispc20/50.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
