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Low Power Decimator Design Using Bit-Serial Architecture for Biomedical Applications
| Content Provider | Semantic Scholar |
|---|---|
| Author | Scholfield, Kristin Chen, Tom |
| Copyright Year | 2012 |
| Abstract | Due to limited battery capacity, electronics in biomedical devices require low power consumption. On the other hand, biomedical devices that integrate multiple functions like sensing, amplification, signal conditioning, signal processing, data storage, etc. have put a greater constraint on power consumption for each functional unit. This paper presents a low power design of a decimator for a sigma-delta ADC for biomedical applications in a commercial 0.18µm CMOS process. Two features help make the design low power: use of bit-serial architecture and use of an ultra-low supply voltage of 0.9V in a 0.18 µm CMOS design. The design interfaces with a sigma-delta modulator with a clock rate of 1MHz. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.iaeng.org/publication/IMECS2012/IMECS2012_pp1185-1189.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
