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Using Unsatisfiable Cores to Estimate Maximum Power in CMOS Combinational Circuits
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2019 |
| Abstract | With the growing integration scales in circuits, the maximum power estimation in CMOS combinational circuits becomes a major design concern for circuit reliability. Previous works formulate it in 0-1 integer linear programming (ILP). However, their approaches do not explicitly express the constraints among variables in the objective function, namely power constraints. The power constraints intuitively characterize the maximum power dissipation. Therefore they cost more time in ILP solving. Motivated by the applications of unsatisfiable cores in optimizing large-scale search problems, we propose a core-guided approach – TEMPO to intuitively express the power constraints. TEMPO includes two processes – refine and abstract, the former for extracting power constraints from unsatisfiable cores and the latter for searching new unsatisfiable cores. The experimental results in the typical MCNC benchmarks show that our approach can improve the speed of solution. Especially, our approach has good performance in challenging benchmarks. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://sysuwanhai.github.io/submit_paper/Using%20Unsatisfiable%20Cores%20to%20Estimate%20Maximum%20Power%20in%20CMOS%20Combinational.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
