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FPGA Implementation of Pipelined CORDIC for Digital Demodulation in FMCW Radar
| Content Provider | Semantic Scholar |
|---|---|
| Author | Mandal, Amritakar Mishra, Rajesh |
| Copyright Year | 2013 |
| Abstract | Abstract— Now-a-days Radar Signal Processing system is gaining a great deal of attention for realization of on-chip programmable signal processor for its real time applications. Application specific systems are being implemented using wide spectrum of Digital Signal Processing (DSP) algorithms. Such is the case for COordinate Rotation DIgital Computer (CORDIC) algorithm which is turned out to be widely researched topic in the field of vector rotated DSP applications. In this paper we have designed an application specific pipelined CORDIC architecture for digital demodulation in low power, high performance FMCW Radar. A complex Digital Phase Locked Loop (DPLL) has been used for digital demodulation. The FPGA implementation of CORDIC based design is suitable because of its inherent high system throughput due to its pipelined architecture where latency is reduced in each of the pipelined stage. Substantial amount of resource utilization has been reduced in proposed design. For better loop performance of first order complex DPLL during demodulation, the convergence of the CORDIC architecture is also optimized. Hardware synthesized result using Cadence design tools are presented. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.infocommunications.hu/documents/169298/393371/2013_2_3_Mandal.pdf |
| Alternate Webpage(s) | http://www.hte.hu/documents/169298/393371/2013_2_3_Mandal.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
