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Simulating the impact of pattern-dependent poly-CD variation on circuit performance
| Content Provider | Semantic Scholar |
|---|---|
| Author | Stine, Brian E. Boning, Duane S. Chung, James E. Ciplickas, Dennis J. Kibarian, John |
| Copyright Year | 1998 |
| Abstract | In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 /spl mu/m 64/spl times/8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell. |
| Starting Page | 552 |
| Ending Page | 556 |
| Page Count | 5 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/66.728551 |
| Volume Number | 11 |
| Alternate Webpage(s) | http://www-inst.eecs.berkeley.edu/~ee290h/sp99/yield_papers/11sm04-stine.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/66.728551 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
