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Reliability in CMOS IC Design : Physical Failure Mechanisms and their Modeling
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2000 |
| Abstract | There are a number of physical failure mechanisms that can affect the reliability of a CMOS ASIC. Some of the common mechanisms can be mitigated by adhering to foundry design rules (Electromigration, Time Dependent Dielectric Breakdown (TDDB), and Hot Carrier Damage). Certain fabrication steps can cause stress that may lead to latent damage that may later reduce the useful lifetime of an ASIC. Contamination with Mobile Ions (most commonly Sodium) will render transistor characteristics unstable and encourage early TDDB. Process Induced Oxide Charging, caused by injection of charge into gate oxides during certain ion etching processes, will reduce TDDB lifetime and cause some transistor degradation similar to Hot Carrier Damage. Metal Stress Migration, which is caused by large thermal coefficient of expansion difference between metal interconnect and inter-level dielectrics (oxides), can lead to voiding of metal lines similar to damage caused by Electromigration. Foundries will expend great effort to control the above fabrication related failure mechanisms by designing the fabrication process to minimize the unnecessary stresses applied to wafers and to maintain an absolutely clean fabrication process to eliminate contamination (by Sodium and other materials). This document will provide an outline of reliability limiting physical mechanisms that are directly influenced by the ASIC designer and also provide some general design for reliability guidelines to ASIC designers. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.mosis.com/files/faqs/tech_cmos_rel.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
