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FPGA Based Design of Pipelined 2-D DCT and Quantization Architecture for JPEG Encoder
| Content Provider | Semantic Scholar |
|---|---|
| Author | Lakshmy, S. |
| Copyright Year | 2015 |
| Abstract | A fast and efficient two dimensional DCT architecture combined with quantization for JPEG image compression is presented to be implemented in FPGA. The proposed method is used for compression of grayscale images. The one dimensional discrete cosine transform is implemented using Arai scaled DCT algorithm and the 1-D DCT architecture is designed using an eight stage pipeline. The design is currently functionally verified, synthesized and is aimed to be tested on a Xilinx Spartan-6 FPGA. The 2-D DCT and quantization architecture uses 684 Slices of Xilinx Spartan 6 FPGA and reaches an operating frequency of 131 MHz. The main advantage of this design is that the proposed architecture can bring about an increase in speed close to 46% when compared to the design in [2]. One input block with 8 x 8 elements of 8 bits is processed in 1130 ns and has an initial pipeline latency of 85 clock cycles. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ijaegt.com/wp-content/uploads/2015/08/409581pp-199-204-lakshmy.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
