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Mapping of Multiple Data Flow Graphs of DSP Applications onto ASIC/Reconfigurable Architectures
| Content Provider | Semantic Scholar |
|---|---|
| Author | Itradat, Awni Hayajneh, Thaier Qatoom, Ahmad |
| Copyright Year | 2013 |
| Abstract | Abstract: This paper presents a novel technique for the mapping of set of DSP applications onto architectures targeting an ASIC/Reconfigurable implementation embedded on the same chip. Synthesis for such a hybrid implementation is carried out by developing a technique to partition the RTL structures corresponding to a set of DSP applications into a fixed base design part suitable for ASIC implementation and a non-base design that varies with the applications and suitable for FPGA implementation. Experimental results reveal that the proposed scheme is efficient in exposing the hidden functional commonality in a set of RTL structures respecting some well-known benchmark problems. We show through a set of test cases that our approach offers significant area saving relative to the state-of-the-art. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://warse.org/pdfs/2013/icctesp08.pdf |
| Alternate Webpage(s) | https://eis.hu.edu.jo/deanshipfiles/pub107755331.pdf |
| Alternate Webpage(s) | http://www.warse.org/pdfs/2013/icctesp08.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
