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High Performance VLSI Architecture for Digital FIR Filter Design
| Content Provider | Semantic Scholar |
|---|---|
| Author | Reddy, S. Lakshmi Kanth |
| Copyright Year | 2015 |
| Abstract | Finite impulse response (FIR) filters are the basic building blocks of many digital signal processing applications. The FIR filter receives a discrete time signal as input and performs the multiplication and addition operations to give the desired filtered discrete time output signal. The real time applications such as radar signal processing and video processing, require dedicated hardware efficient FIR filters to be implemented with higher clock frequencies. Nowadays, many battery operated devices such as hearing aids and mobile phones also use FIR filters as it offers stability and linear phase response. As these devices are power hungry devices, a low power FIR implementation is required for these applications. Hence, to meet the ever demanding high speed and low power devices, new methods for hardware efficient FIR filter architectures are proposed in this thesis. The FIR filter implementations are classified as fixed coefficient and programmable coefficient filter architectures. The hardware implementations of fixed and programmable filter architectures are different from each other. In this thesis, two new approaches for fixed coefficient and one improved architecture for programmable coefficient filter are proposed. In both fixed and programmable filter implementations, multiplier is the most expensive component in terms of hardware. In fixed coefficient filter implementation, replacement of the multiplier with the shift and adder circuits is a well-known technique. The adders in this approach are dependent on the number of one’s or signed-power-of-two (SPT) terms present in each filter coefficient. In the first method proposed in this thesis, differential evolution algorithm is used for reducing the number of SPT terms in filter coefficients. Then, with the help of a common subexpression elimination algorithm the number of adders is further minimized for efficient filter implementation. The performance of the proposed filter shows better results in comparison to some of the recently published work in terms |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ietd.inflibnet.ac.in:8080/jspui/bitstream/10603/182978/1/2007phxf430_thesis.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
