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VLSI DESIGN OF LOW POWER HIGH SPEED DOMINO LOGIC Ms
| Content Provider | Semantic Scholar |
|---|---|
| Author | Agrawal, Rakhi R. Ladhake, Siddharth A. |
| Copyright Year | 2012 |
| Abstract | Simple to implement, low cost designs in CMOS Domino logic are presented. These designs require less transistors and are full Domino logic compatible while they attain better performance compared to the standard Domino logic implementations. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. The novel feature of dynamic circuits is often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. This paper compares static CMOS, domino (dynamic) logic design implementations. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijmra.us/project%20doc/IJMIE_MARCH2012/IJMRA-MIE878.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
