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Nanocharacterization Challenges in a Changing Microelectronics Landscape
| Content Provider | Semantic Scholar |
|---|---|
| Author | Brillouet, Michel |
| Copyright Year | 2011 |
| Abstract | As the microelectronics industry enters the “nano”‐era new challenges emerge. Traditional scaling of the MOS transistor faces major obstacles in fulfilling “Moore's law”. New features like strain and new materials (e.g. high k—metal gate stack) are introduced in order to sustain performance increases. For a better electrostatic control, devices will use the third dimension, e.g., in gate‐all‐around nanowire structures. Due to the escalating cost and complexity of sub‐28 nm technologies fewer industrial players can afford the development and production of advanced CMOS processes and many companies acknowledge the fact that the value in products can also be obtained in using more diversified non‐digital technologies (the so‐called “More‐than‐Moore” domain). This evolving landscape brings new requirements—discussed in this paper—in terms of physical characterization of technologies and devices. |
| Starting Page | 15 |
| Ending Page | 23 |
| Page Count | 9 |
| File Format | PDF HTM / HTML |
| DOI | 10.1063/1.3657861 |
| Alternate Webpage(s) | http://www.nist.gov/pml/div683/conference/upload/1-1.pdf |
| Alternate Webpage(s) | https://doi.org/10.1063/1.3657861 |
| Volume Number | 1395 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
