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New Interconnect Technologies in On-Chip Communication
| Content Provider | Semantic Scholar |
|---|---|
| Abstract | W ITH Moore's Law continuing to increase the number of transistors, the number of cores on a single chip is continuing to increase as well. The International Technology Roadmap for Semiconductors (ITRS) projects that device scaling will continue but the interconnect will not scale at the same rate. As a result, communication or movement of data is becoming the bottleneck of manycore systems and often determines the scalability, both in terms of cost and performance. To overcome the limitations of conventional electrical signaling communication, alternative technologies have been recently proposed and will not only impact how data is communicated on-chip but also the system design. The on-chip communication or the network-on-chip architecture (NoC) needs to be designed efficiently to properly exploit these new interconnect technologies to enable the additional computation capability of manycore processors to be properly leveraged. The purpose of this special issue is to report on recent advances in new interconnect technologies and the design of on-chip communication architecture and circuits that leverage these new technologies. In particular, this special issue fo-cuses on enabling circuit and system designs that exploit these new technologies to create cost-efficient communication in manycore processors. Recent advances in devices have shown the feasibility of some alternative technologies for on-chip communication. However, it still remains an open problem in terms of how these individual components can be scaled through different circuit and architecture designs to create a system that fully leverages the benefit of these technologies while minimizing the overall cost of the system. New interconnect technologies often introduce additional cost in terms of area and/or power consumption and the trade-off from these technologies needs to be properly explored, compared with the state-of-the-art advances in conventional, electrical signaling. Some technologies while providing significant benefits (e.g., lower latency and higher bandwidth) can introduce additional challenges that did not exist with conventional electrical sig-naling, such as reliability or thermal issues. The advances in different interconnect technologies present different challenges, which include determining the appropriate architectures (both microarchitecture and system architecture) that can properly exploit these new technologies. The different technologies can lead to different optimal topology for the network on chip , compared with conventional electrical signaling. The new interconnect technologies can also enable communication organization that was not feasible with electrical sig-naling—such as providing a scalable, global bus or providing a fully-connected network. Some of the technologies can be combined to further increase the benefits—for … |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://web.kaist.ac.kr/~jjk12/papers/2012JETCAS.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
