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FPGA Implementation of Multiplier for Floating- Point Numbers Based on IEEE 754-2008 Standard
| Content Provider | Semantic Scholar |
|---|---|
| Author | Ibrahimy, Muhammad Ibn |
| Copyright Year | 2015 |
| Abstract | This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis etc. Implementation of floating-point multiplication is handy and easy for high level language. However it is a challenging task to implement a floating-point multiplication in hardware level/low level language due to the complexity of algorithm. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floating-point multiplier module using Verilog Hardware Description Language (HDL). Electronic Design Automation (EDA) tool of Altera Quartus II has been used for floating-point multiplier. The hardware implementation has been done by downloading the Verilog code onto Altera DE2 FPGA development board and found a satisfactory performance. |
| Starting Page | 1 |
| Ending Page | 6 |
| Page Count | 6 |
| File Format | PDF HTM / HTML |
| DOI | 10.22385/jctecs.v1i0.2 |
| Volume Number | 1 |
| Alternate Webpage(s) | https://jctecs.com/index.php/com/article/download/2/1 |
| Alternate Webpage(s) | https://doi.org/10.22385/jctecs.v1i0.2 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
