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United States Patent ( 10 ) Patent No . : US 6 , 297 , 095 B 1
| Content Provider | Semantic Scholar |
|---|---|
| Author | Chitra Subramanian, K. |
| Copyright Year | 2017 |
| Abstract | (*) Notice: Subject to any disclaimer, the term of this A Semiconductor memory device with a floating gate that patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days. includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of Such a device are presented. The device is formed by first providing a semiconductor 21 Ap1. No.: 09.1596.399 (21) Appl. No.: 09/596, substrate (12) upon which a tunnel dielectric layer (14) is (22) Filed: Jun. 16, 2000 formed. A plurality of nanoclusters (19) is then grown on the (51) Int. Cl." ............................................... H01L 21/336 tunnel dielectric layer (14). After growth of the nanoclusters (52) U.S. Cl. ............................................. 438/257; 438/197 (21), a control dielectric layer (20) is formed Over the (58) Field of Search .............................. 438/97, 197,211, nanoclusters (21). In order to prevent oxidation of the 438/257, 263, 264, 265, 680, 266, 165, formed nanoclusters (21), the nanoclusters (21) may be 166, 491, 594, 770, 775 encapsulated using various techniques prior to formation of the control dielectric layer (20). Agate electrode (24) is then 56 References Cited (56) formed over the control dielectric (20), and portions of the U.S. PATENT DOCUMENTS control dielectric, the plurality of nanoclusters, and the gate 5,886,368 3/1999 Forbes et al. .......................... 25777 dielectric that do not underlie the gate electrode are selec 6,090,666 * 7/2000 Ueda et al. ... ... 438/257 tively removed. After formation of spacers (35), source and 6,140,181 * 10/2000 Forfes et al... ... 438/257 drain regions (32,34) are then formed by implantation in the 6,166,401 12/2000 Forbes .................................... 257/77 Semiconductor layer (12) Such that a channel region is OTHER PUBLICATIONS formed between the source and drain regions (32, 34) Wahl et al., “Write, Erase and Storage Times in Nanocrystal underlying the gate electrode (24). Memories and the Role of Interface States,” IEEE, pp. 15.4.1-15.44 (1999). 17 Claims, 4 Drawing Sheets |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://patentimages.storage.googleapis.com/c3/4c/0e/aa355f92437d88/US6297095.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Patent |
