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Technology Mapping Targeting Routing Congestion under Delay Constraints
| Content Provider | Semantic Scholar |
|---|---|
| Author | Shelar, Rupesh S. Saxena, Prashant Sapatnekar, Sachin S. |
| Copyright Year | 2005 |
| Abstract | Routing congestion has become a serious concern in today's VLSI designs. To address the same, we propose a technology ma pping algorithm that minimizes routing congestion under delay constraints in this paper. The algorithm employs a dynamic programming framework in the matching phase to generate probabilistic congestionmaps for all the matches. These congestion maps are then utilized to mini m ze routing congestion during the covering, which preserves the delayoptimality of the solution using the notion of slack. Experimental result s on benchmark circuits in a 100 nm technology show that the algorithm can improve track overflows by 59%, on an average, as compared to conventi onal technology mapping, while satisfying delay constraints. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ece.umn.edu/users/sachin/jnl/tcad06rs.pdf |
| Alternate Webpage(s) | http://www.ece.umn.edu/~sachin/jnl/tcad06rs.pdf |
| Alternate Webpage(s) | http://www.ee.umn.edu/users/sachin/jnl/tcad06rs.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
