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128-Word Register Files on a Dual-Core Itanium-Family Processor
| Content Provider | Semantic Scholar |
|---|---|
| Author | Fetzer, Eric S. Wang, Lei-Gao Jones, J. |
| Copyright Year | 2000 |
| Abstract | Multi-threaded microprocessors require multiple sets of register files to process concurrent instruction streams. This significantly complicates the register-file (RF) design and exacerbates reliability problems. This paper describes the dual-threaded, 18-port (8read, 10-write), 128word × 82b floating-point register file (FRF), and the 22-port (12-read, 10-write), 128 × 65b integer register file (IRF) of the processor-code named Montecito [1]. A memory circuit is designed that consists of two storage cells, each bit accessible by two different threads. A charge-compensation technique is introduced to mitigate charge-sharing noise induced by threadswitch events. The dual-threaded implementation essentially doubles the number of memory cells and the RF becomes even more susceptible to errors caused by high-energy particles. A low-complexity parity-checking scheme is embedded into each register to provide soft error detection. The current design also integrates several power-saving features to achieve energy-efficiency and reliable operation. |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/isscc.2005.1494029 |
| Alternate Webpage(s) | http://saluc.engr.uconn.edu/refs/memory/current/fetzer05themulti.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
