NDLI: Timing Driven Gate Duplication for Delay

Please wait, while we are loading the content...

Timing Driven Gate Duplication for Delay

Content Provider	Semantic Scholar
Author	Srivastava, O. Kastner, Ryan Chen, Chunhong Department, Majid Sarrafzadeh
Copyright Year	2007
Abstract	In the past few years gate duplication has been studied as a strategy for cutset minimization in partitioning problems .This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary in-puts(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's rst component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and nal traversal is again from PO to PI in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We proved the problem of partitioning a fanout set between a node and it's replica to be NP-Complete 2]. Hence our proposed algorithm uses a heuristic for solving this problem which is optimal (locally) in speciic cases. We report delay improvements as high as 8% over highly optimized results generated by SIS (generated by using map-n 1-AFG option of the mapper). The potential of the algorithm is also demonstrated by reporting average delay improvements of around 26.2% after a good minimum delay technology mapper (map-n 1 option). The results show that along with other optimization strategies, gate duplication can be used for meeting the stringent delay constraints in todays multi-million gate designs.
File Format	PDF HTM / HTML
Alternate Webpage(s)	http://www.cs.ucla.edu/~chchen/public/ankur_TCAD.ps
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in