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Design and implementation of an RSFQ switching node for petaflops networks
| Content Provider | Semantic Scholar |
|---|---|
| Author | Yorozu, Shinichi Zinoviev, D. Yu. Sazaklis, George N. |
| Copyright Year | 1999 |
| Abstract | This work is part of a project to design a petaflops-scale computer using a hybrid technology multi-threaded architecture (HTMT). A high-bandwidth low-latency switching network (CNET) based on RSFQ logic/memory family comprises the core of the superconductor part of the HTMT system, interconnecting 4,096 processors. We present a preliminary low-level design and partial experimental implementation of a multi-credit RSFQ network switching node with the estimated throughput of 7/spl middot/10/sup 10/ 85-bit-parallel packets per second, service latency of 109 ps, and dissipated power of 4.6 mW. |
| Starting Page | 3557 |
| Ending Page | 3560 |
| Page Count | 4 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/77.783798 |
| Volume Number | 9 |
| Alternate Webpage(s) | https://doi.org/10.1109/77.783798 |
| Journal | IEEE Transactions on Applied Superconductivity |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
