Loading...
Please wait, while we are loading the content...
Similar Documents
GoldMine : Automatic Assertion Generation and Coverage Closure in Design Validation
| Content Provider | Semantic Scholar |
|---|---|
| Author | Sheridan, David Liu, Lingyi Vasudevan, Shobha |
| Copyright Year | 2011 |
| Abstract | We present GOLDMINE, a methodology for generating assertions automatically. Our method involves a combination of data mining and static analysis of the Register Transfer Level (RTL) design. The RTL design is first simulated to generate data about the design’s dynamic behavior. The generated data is then mined for ”candidate assertions” that are likely to be invariants. These candidate assertions are then passed through a formal verification engine to filter out the spurious candidates. The assertions that are attested as true by the formal engine are system invariants. The counter-examples generated by the formal verification can then we used as feedback to the decision tree algorithm to increase the design coverage. These assertions are evaluated by a process of designer ranking that can be provided as feedback to the data mining engine. We present results of using GoldMine for assertion generation of the Rigel 1000+ core processor. Our results show that GoldMine can generate complex, high coverage assertions in RTL, thereby minimizing human effort in this process. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://events.dvcon.org/2011/proceedings/papers/02p_5.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
