Loading...
Please wait, while we are loading the content...
Similar Documents
Variation Tolerant Asynchronous FPGA
| Content Provider | Semantic Scholar |
|---|---|
| Author | Shang, Dl Yakovlev, Alexandre |
| Copyright Year | 2011 |
| Abstract | This paper describes the realization of an interconnect Delay Insensitive (DI) FPGA architecture with distributed asynchronous control. This architecture maintains the basic block structure of traditional FPGAs allowing the potential use of existing FPGA design tools in block design. This asynchronous FPGA architecture is mainly aimed at tolerating the unpredictable delay variations caused by process and environment variations in current and future VLSI technology nodes and also targets low power operations, including modes such as dynamic voltage scaling and variable Vdd, as in applications featuring energy harvesting. This is achieved by making the longer inter-block interconnects DI, keeping the computational logic single-rail, and removing global clocks. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://async.org.uk/tech-reports/NCL-EECE-MSD-TR-2010-163.pdf |
| Journal | FPGA 2011 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
