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An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications
| Content Provider | Semantic Scholar |
|---|---|
| Author | Varshney, Vikrant Nagaria, Rajendra Kumar |
| Copyright Year | 2019 |
| Abstract | Currently, dynamic comparator approach necessitates in high-speed and power efficient analog-to-digital converter applications due to its high latching speed and ultra-low power consumption. In this paper, a~novel dynamic comparator is proposed to reduce latch delay and offset. The comparator benefits from add-on cross-coupled transistors in latch structure and unbalanced clocks to enhance comparison speed and to lessen input offset voltage occurred due to mismatch in cross-coupled circuits in latch stage. The derivations for delay and input offset voltage are presented for proposed dynamic comparator with meticulous Monte-Carlo simulations. The results are verified by simulations in CADENCE SPECTRE at 1V supply voltage and 90nm CMOS technology. A~comparative analysis between the proposed dynamic comparator and the previous reported comparators has been presented. It is observed that the delay is reduced up to 46% and 6% as compared to conventional and two phase dynamic comparator, respectively. Moreover, the proposed design consumes 53.36muW power only. The Monte-Carlo simulation shows that the standard deviation of input offset voltage is 10.8~mV which is 12% and 77% of conventional and two phase dynamic comparator, respectively. |
| Starting Page | 446 |
| Ending Page | 458 |
| Page Count | 13 |
| File Format | PDF HTM / HTML |
| DOI | 10.15598/aeee.v17i4.3326 |
| Volume Number | 17 |
| Alternate Webpage(s) | http://advances.utc.sk/index.php/AEEE/article/download/3326/488488599 |
| Alternate Webpage(s) | https://doi.org/10.15598/aeee.v17i4.3326 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
