System-on-chip test parallelization under power constraints (2001)

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Design of system-on-a-chip test access architectures under place-and-route and power constraints

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Design of system-on-a-chip test access architectures under place-and-route and power constraints

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Design of System-on-a-Chip Test Access Architectures under Place-and-Route and Power Constraints (2000)

Design of System-on-a-Chip Test Access Architectures under Place-and-Route and Power Constraints (2000)

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An integrated system-on-chip test framework.

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A simulated annealing algorithm for system-on-chip test scheduling with power and precedence constraints ∗ (2008).

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Power-Aware Mapping for Network-on-Chip Architectures under Bandwidth and Latency Constraints

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An Integrated System-On-Chip Test Framework (2001)

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