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Wideband DOA Estimation Algorithms for Multiple Moving Sources using Unattended Acoustic Sensors
| Content Provider | Semantic Scholar |
|---|---|
| Author | Pok, Dany Chen, Chia-Ching Montgomery, J. F. Tsui Grajal, Jesús Azquez, Bí Opez-Risueño, L. Burgos, J. Munos Asensio Sanchez, L. Opez-Vallejo, M. Opez-Barrio, L. Yunnan Parhi Szedő, Gábor Yang, Vendel Dick Cooley, James W. Tukey Yuezhong Harris, F. J. Sanz-Osorio |
| Copyright Year | 2008 |
| Abstract | Tsui, J. Chip design for monobit receiver. IEEE Transactions on Microwave Theory and Techniques, 45 (Dec. 1997). [12] Grajal, J., Blázquez, R., López-Risueño, G., Sanz, J. M., Burgos, M., and Asensio, A. Analysis and characterisation of a monobit receiver for electronic warfare. IEEE Transactions on Aerospace and Electronic Systems, 39, 1 (Jan. 2003). [13] Sanchez, M., Garrido, M., López-Vallejo, M., and López-Barrio, C. Automated design space exploration of FPGA-based FFT architectures based on area and power estimation. In Proceedings of IEEE International Conference on Field Programmable Technology (FPT 2006), 2006, 127—134. [14] Yun-Nan, C., and Parhi, K. An efficient pipelined FFT architecture. IEEE Transactions on Circuits and Systems II, 50, 6 (2003), 322—325. [15] Sansaloni, T., Pérez-Pascual, A., and Valls, J. Area-efficient FPGA-based FFT processor. Electronics Letters, 39, 19 (2003). [16] Szedo, G., Yang, V., and Dick, C. High-performance FFT processing using reconfigurable logic. In 35 Asilomar Conference on Signals, Systems and Computers, 2001, 1353—1356. [17] Cooley, J. W., and Tukey, J. W. An algorithm for machine calculation of complex Fourier series. Mathematics of Computation, 19 (1965). [18] Volder, J. E. The CORDIC trogonometric computing technique. IRE Transactions on Electronic Computing, (1959). [19] Jun, W., Shiyi, M., and Yuezhong, W. Design and implementation of a high speed vector processor for real-time SAR imaging. In Proceedings of CIE International Conference on Radar, 2001. [20] Xilinx Inc. Xilinx LogiCore: Fast Fourier Transform v3.1, 2004. http://www.xilinx.com/products/Broadband/. [21] Nordin, G., Milder, P. A., Hoe, J. C., and Püschel, M. Automatic generation of customized discrete Fourier transform IPs. In Proceedings of Design Automation Conference (DAC), 2005. [22] Li, F., Chen, D., He, L., and Cong, J. Architecture evaluation for power-efficient FPGAs. In Proceedings of ACM International Symposium on Field Programmable Gate Arrays, 2003, 175—184. [23] Curd, D. Power consumption in 65 nm FPGAs, 2006, white paper: Virtex-5 Family of FPGAs. http://www.xilinx.com. [24] Skolnik, M. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.engr.colostate.edu/ece/faculty/azimi/pdf/journals/ECEmra00068.pdf |
| Alternate Webpage(s) | http://www-personal.k-state.edu/~nickrose/files/AzimiRoseveare2008-AES-Wideband%20DOA.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
