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IP Session 7C: Design for Yield and Manufacturability
| Content Provider | Semantic Scholar |
|---|---|
| Author | Shoukourian, Samvel K. |
| Copyright Year | 2008 |
| Abstract | Increased manufacturing variability in leading-edge process technologies requires new paradigms and solution technologies for yield optimization. SoC manufacturability and yield entails design-specific optimization of the manufacturing, and thus enhanced communications across the design-manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) methodologies and tools have been proposed in recent years. Some of these tools are leveraged during backend design, others are applied post-GDSII, and still others are applied post-design, from reticle enhancement and lithography through wafer sort, packaging, final test and failure analysis. DFY and DFM can dramatically impact the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using DFY and DFM solutions is an investment, and choosing the most cost effective one(s) requires careful analysis of integration and schedule overheads, versus quantified benefits. This session analyzes the key trend and challenges, and provides a set of innovative DFM and DFY practices used for today's SoC designs. |
| Starting Page | 240 |
| Ending Page | 240 |
| Page Count | 1 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/vts.2008.73 |
| Alternate Webpage(s) | https://csdl.computer.org/csdl/proceedings/vts/2008/3123/00/3123a240.pdf |
| Journal | 26th IEEE VLSI Test Symposium (vts 2008) |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
