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High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1 . 3 GHz Citation
| Content Provider | Semantic Scholar |
|---|---|
| Author | Chen, Xiangyu Lee, Kyeong-Jae Akinwande, Deji Close, Gael F. Yasuda, Shinichi Paul, Bipul C. Fujita, Shinobu Kong, Jing Wong, H.-S. Philip |
| Copyright Year | 2009 |
| Abstract | We have successfully experimentally integrated graphene interconnects with commercial 0.25μm technology CMOS ring oscillator circuit using conventional fabrication techniques, and demonstrated high speed on-chip graphene interconnects that operates above 1GHz. Introduction Graphene has been considered as one of the most promising materials for future interconnects technology [1]. Theoretical studies have shown that graphene has lower resistivity, higher maximum current density, and lower capacitance compared to copper in nanoscale dimensions [2]. Graphene also potentially offers advantages such as simpler fabrication processes and better material control and reproducibility, compared with multi-walled carbon nanotubes (MWCNT). Despite the exciting theoretical predictions and measurements performed at DC [2,3], experimental demonstration of high speed signaling in graphene interconnects has not been made. There is no report yet on the integration of graphene with CMOS technology either. This paper presents 1) the first monolithic integration of graphene with commercial CMOS technology, and 2) the first experimental demonstration of high-speed signaling of on-chip graphene interconnects. Characterization results showed operation frequency up to 1.3 GHz. Device Fabrication (1) Graphene synthesis and transfer Large area graphene films are grown by chemical vapor deposition (CVD), and then transferred to a 5mm×5mm CMOS chip following the procedure developed by Reina et al. [4]. The graphene synthesis and transfer is described below in brief. A 500nm Ni film is evaporated on a SiO2/Si substrate and thermally annealed. The growth is carried out for 5 minutes at 1000°C, with 5 sccm and 1300 sccm flow of CH4 and H2, respectively. After the growth process, poly(methyl methacrylate) (PMMA) is spin-coated on the graphene/Ni film. The substrate is subsequently placed in a 10% HCl aqueous solution, which etches away the underlying Ni film and releases the graphene film. Once the PMMA/graphene film is placed on the target substrate, the PMMA layer is removed by acetone [4]. The described process flow of material synthesis and transfer is shown in Fig. 1. An average sheet resistance of ~700ohms/sq was extracted for graphene before post-transfer process by transferring graphene films onto SiO2/Si test substrates. (2) Integration with CMOS circuit The CMOS chip was fabricated using a 0.25μm CMOS technology. Each of the arrays of 256 ring oscillators was designed with a missing interconnect wire onto which a graphene interconnect wire was subsequently integrated. Fig. 2 illustrates the process flow for post-transfer processing. The |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://dspace.mit.edu/openaccess-disseminate/1721.1/71870 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
