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Design of a low-power, reconfigurable digital front-end for a multimode SDR handset.
| Content Provider | Semantic Scholar |
|---|---|
| Author | Michael, Navin |
| Copyright Year | 2012 |
| Abstract | Emerging communication paradigms like opportunistic spectrum access and wireless heterogeneous networks impose a high degree of flexibility on the underlying physical layer hardware of the mobile terminal. A software implementation of the radio baseband algorithms on an instruction set architecture (ISA) offers the highest degree of flexibility and hardware reusability, since the reconfiguration of the terminal for a new standard involves a mere change of software code. However the power efficiencies of ISAs have not scaled to the point where the entire baseband computations of a mobile handset can be performed in software. The computationally intensive signal processing tasks in the radio baseband have to be accelerated in hardware. Dedicated hardware (HW) accelerator cores have a power efficiency which is several orders higher than a software implementation and hence, have been extensively used for accelerating the computationally intensive tasks like channelization and decoding. HW accelerators, however, are inflexible in general and are optimized for a single specification. Incorporating flexibility necessarily incurs both an area and power penalty. The growing need for supporting multiple wireless standards with heterogeneous throughput and mobility requirements in a small form factor mobile handset with a limited silicon area requires the accelerator cores to be flexible and reusable in addition to being power efficient. The goal of this thesis is to evolve a framework for designing flexible, power efficient and area efficient multistandard channelization accelerators in the digital front-end of software defined radio (SDR) handsets. SDR is a disruptive paradigm for designing flexible, multimode radios, in which a significant portion of the radio signal processing load is pushed towards the digital domain, where one has the advantages of easier reprogrammability and more mature power optimization strategies. The digital front-end acts as the interface between the analog-to-digital converter and the subsequent digital baseband blocks. It performs the channelization function, which is one of the most computationally intensive kernels in the radio receiver chain. In a flexible radio, the channelization accelerators should be capable of selecting a channel of arbitrary bandwidth and also perform a sample rate conversion (SRC) operation by arbitrary integral or rational factors. They should also provide sufficient attenuation of interferers, blockers and out of band quantization noise, so that that the co-channel interference due to aliasing, and the carrier to noise ratio are below the permissible limits for all modes of operation. In general the area and power overheads of a flexible accelerator are a function of the granularity of hardware reuse across multiple modes. Reusing hardware blocks at coarser levels of granularity offers more opportunities for high level synthesis behavioral optimizations to reduce the area and power. Reusability of coarse grained operators also reduces the amount of reconfiguration data required to parameterize the accelerator. The channelization tasks of channel selection, interferer attenuation and sample rate conversion can be reduced to a set of filtering and decimation operations. Traditional flexible filter acceleration strategies range from the Velcro approach, where multiple standard specific filters are implemented in parallel with no hardware sharing/reuse, to the filter coprocessor approach, which reuses the same set of coarse grained word-level datapath operators. The former method incurs a high area and leakage power overhead, while the latter method incurs a significant dynamic power overhead. The higher leakage power overhead is particularly significant in battery powered mobile devices which spend most of the time in standby mode, where leakage power dominates the overall power consumption. The filtering and decimation tasks can be efficiently performed by partitioning the decimation load into multiple stages. This allows low order filters to operate at high sampling rates, and high order filters to operate at low sampling rates. The filter stages in the multistage decimation filter represent a naturally coarse level of granularity for identifying hardware reuse opportunities. However there are several bottlenecks to directly reusing fixed hardwired filter stages across multiple standards. Firstly there are several ways in which the decimation load may be partitioned across multiple stages. Arbitrarily factorizing the decimation factor for each standard would make the task of finding shared decimation stages difficult. Secondly there exists specialized filter structures like the non recursive cascaded integrator comb filter, the halfband filter, and the Farrow structure which are much more efficient than generic FIR decimation stages, but are effective only at certain stages in the decimation chain, or for certain decimation factors. Hence an efficient and flexible channelization strategy should seek to minimize the computational load by maximizing the use of specialized filter stages, and identify opportunities for hardwiring and reusing filter stages across multiple standards. The first contribution of this thesis is an analysis of the area, power and reconfiguration latency overheads incurred, when flexibility is incorporated in an accelerator. These overheads are referred to as the flexibility penalty in this thesis. The factors that affect the flexibility penalty components and their impact in a practical energy constrained, resource constrained mobile radio is analyzed. The above components are a function of the granularity of hardware reuse across different modes. We have analyzed the flexibility penalty of traditional filter accelerator designs with respect to the granularity of hardware reuse in the design. The second contribution of this thesis is a sample rate conversion factorization strategy, that allows arbitrary integral or rational decimation load to be partitioned into fixed regular form. This allows the band edge and stopband attenuation of all the filter stages prior to the last stage to be modified in a manner which allows them to be hardwired and reused across multiple standards with very low reconfiguration overheads. Since it reuses hardware at a much coarser level of granularity than filter coprocessors, it has a much lower dynamic power consumption and a much lower area overhead than a Velcro style accelerator. Experimental synthesis results have been used to demonstrate the area and power advantage of the proposed accelerator over traditional designs. The runtime parameterizations issues and clocking mechanisms for the proposed channelization accelerator have also been analyzed. The third contribution of this thesis is a strategy for reducing the power penalty of the filter stages than need to be reprogrammable in the proposed architecture. The need for generic MAC units in programmable filters results in a much higher dynamic power consumption, when compared to the hardwired filter stages. In this thesis, a class of programmable time-shared FIR filters based on fast filter algorithms is proposed, that can trade area for increased timing slack more efficiently than traditional direct form structure based time-shared filters, with increasing levels of parallelism. The increased timing slack in the proposed structure provides more room for supply and threshold voltage scaling, which in turn can be used to reduce all the major nanoscale CMOS power consumption components. |
| File Format | PDF HTM / HTML |
| DOI | 10.32657/10356/48073 |
| Alternate Webpage(s) | https://repository.ntu.edu.sg/bitstream/handle/10356/48073/TsceG0700103L.pdf;sequence=1 |
| Alternate Webpage(s) | https://doi.org/10.32657/10356%2F48073 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
