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A Timing-Driven Global Router for Symmetrical Array Based FPGAs
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2007 |
| Abstract | In this paper, we present a timing-driven global router for symmetrical array-based architecture FPGAs. The routing resources in symmetrical array based FPGAs consist of segments of various lengths. The timing constraints are speciied as delay bounds on source-sink pairs of nets. The algorithm proceeds in a hierarchical top-down manner and is able to utilize various routing segments with global consideration in order to meet the timing constraints. Furthermore , the algorithm can be extended to perform detailed routing simultaneously with global routing. Experimental results on real circuits show that the algorithm is promising in satisfying the timing constraints compared with the conventional global router. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.cs.utexas.edu/ftp/pub/techreports/tr94-22.ps.gz |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
