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Statistical Power Profile Correlation for Realistic Thermal-aware Floorplanning
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2007 |
| Abstract | In nano-based microarchitectural design, achieving higher clock frequency is confronted with thermal restrictions especially with the presense of temperature-variant leakage power. While amodule temperature depends both on power density and the thermal coupl ing with the neighboring blocks, thermal-aware floorplans have beenintroduced to reduce peak temperature. The major drawback is that the thermal behavior is input application dependent. Considering aver age or peak power density may lead either to underestimation of the ther mal crisis or to degradation in performance. To provide more realistic temperature estimation, we propose to apply multiple power profiles during floorplanning. Using the proposed statistical methods to de t rmine the closeness between the power profiles, we apply our clusterin g algorithm to identify power profiles with close thermal behavior. We then generate a set of power profiles asleader power profiles to be incorporated in a thermal-aware floorplanner. Our empirical results show that using the single leader power profile (average or peak) leads to37% degradation in critical wire delay and 20% degradation in wire length, compared to using the multiple leader power profiles. Our correlation metrics coupled with the clustering algorithm gives comparable improvements in the floorplanning with improved runtime as well. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ics.uci.edu/~lsinghal/aspdac08.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
