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Harnessing FPGA technology for rapid circuit debug
| Content Provider | Semantic Scholar |
|---|---|
| Author | Hung, Eddie |
| Copyright Year | 2013 |
| Abstract | Electronic devices have come to permeate every aspect of our daily lives, and at the heart of each device is one or more integrated circuits. State-of-the art circuits now contain several billion transistors. However, designing and verifying that these circuits function correctly under all expected (and unexpected) operation conditions is extremely challenging, with many studies finding that verification can consume over half of the total design effort. Due to the slow speed of logic simulation software, designers increasingly turn to circuit prototypes implemented using field-programmable gate array (FPGA) technology. Whilst these prototypes can be operated many orders of magnitude faster than simulation, on-chip instruments are required to expose internal signal data so that designers can root-cause any erroneous behaviour. This thesis presents four contributions to enable rapid and effective circuit debug when using FPGAs, in particular, by harnessing the reconfigurable and prefabricated nature of this technology. The first contribution presents a post-silicon debug metric to quantify the effectiveness of trace-buffer based debugging instruments, and three algorithms to determine new signal selections for these instruments. Our most scalable algorithm can determine the most influential signals in a large 50,000 flip-flop circuit in less than 90 seconds. The second contribution of this thesis proposes that debug instruments be speculatively inserted into the spare capacity of FPGAs, without any user intervention, and shows this to be feasible. This proposal allows designers to extract more trace data from their circuit on every debug turn, ultimately leading to fewer debug iterations. The third contribution presents techniques to enable faster debug turnaround, by using incrementalcompilation methods to accelerate the process of inserting debug instruments. Specifically, our incremental optimizations can speed up this procedure by almost 100X over recompiling the FPGA from scratch. |
| File Format | PDF HTM / HTML |
| DOI | 10.14288/1.0074092 |
| Alternate Webpage(s) | https://open.library.ubc.ca/media/download/pdf/24/1.0074092/3 |
| Alternate Webpage(s) | https://doi.org/10.14288/1.0074092 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
