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Real-Time H.264/AVC Entropy Encoder Hardware Architecture in Baseline Profile
| Content Provider | Semantic Scholar |
|---|---|
| Author | Asma, Ben Hamida Salah, Dhahri Abdelkrim, Zitouni |
| Copyright Year | 2017 |
| Abstract | In this paper, we present a new hardware architecture of an entropy encoder for an H.264/AVC video encoder. The proposed design aims to employ a parallel module at a pre-encoding stage to reduce a critical path. Additionally, the arithmetic table elimination method is used to eliminate the memory cost. Besides, the reduction in the size of VLC tables offers area saving. This architecture is synthesized on an FPGA Virtex IV. The simulation results show that this design can operate up to 234 MHz, which allows processing a 4CIF video format in real time. |
| File Format | PDF HTM / HTML |
| DOI | 10.14569/IJACSA.2017.080339 |
| Volume Number | 8 |
| Alternate Webpage(s) | http://thesai.org/Downloads/Volume8No3/Paper_39-Real-Time_H.264AVC_Entropy_Encoder_Hardware.pdf |
| Alternate Webpage(s) | https://doi.org/10.14569/IJACSA.2017.080339 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
