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RV-IOV : Tethering RISC-V Processors via Scalable I / O Virtualization
| Content Provider | Semantic Scholar |
|---|---|
| Author | Vega, Luis Taylor, Michael Bedford |
| Copyright Year | 2017 |
| Abstract | Recent interest in open source instruction set architecture (ISA) such as RISC-V has opened new horizons for computer systems research across operating systems, compilers, and hardware architectures. One fundamental aspect catalyzing these innovations is the ability to emulate a complete system. This allows researchers evaluate their ideas on real hardware without the hassle of building infrastructure. One interesting RISC-V core generator available is the Rocket chip generator [1], which generates RISC-V implementations using customizable parameters. There are currently three emulation systems for the Rocket core available to the community: Zybo, Zedboard, and ZC706. These systems are based on a heterogeneous multiprocessing chip composed of a general purpose processor running a host, aka front-end server, and programmable logic where the actual Rocket core is implemented. The drawback of these systems is the tight integration between the Rocket core and the host. This result in challenges when (i) a Rocket core is implemented in ASICs, and (ii) a Rocket core configuration requires more resources than available in current emulation systems. We propose hardware support, RV-IOV, that overcome these limitations and increase the number of prototyping targets for Rocket cores. RV-IOV decouples Rocket cores from the host using I/O virtualization and enables cores to be implemented in ASICs or larger FPGAs. We describe a case of study implementing RV-IOVs to enable five Rocket cores that share the same host in a novel system-on-chip design called Celerity [22], which is a tiered parallel RISC-V architecture implemented in TSMC 16 nm. Additionally, the system is further evaluated against multi-FPGA system, based on the Zedboard and an external open source emulation board called DoubleTrouble [4]. Finally, we measure performance overhead for two systems using seven benchmarks. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://homes.cs.washington.edu/~vegaluis/pdf/carrv17_vega_rviov_paper.pdf |
| Alternate Webpage(s) | https://homes.cs.washington.edu/~vegaluis/pdf/carrv17_vega_rviov_slides.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
