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High-Accuracy Digital to Analog Converter Dedicated to Sine-Waveform Generator for Avionic Applications
| Content Provider | Semantic Scholar |
|---|---|
| Author | Karimian-Sichany, Masood |
| Copyright Year | 2013 |
| Abstract | RESUME De nos jours, malgre les avancees remarquables de la microelectronique, les systemes avioniques emploient essentiellement des technologies vieillissantes afin de repondre aux normes de securite exigeantes des systemes avioniques. La nouvelle generation d'avionique modulaire integree (AMI) des More Electric Aircrafts (MEA), necessite des architectures de reseaux stables et fiables, employant des modules electroniques integrables modernes qui restent a etre concus et developpes. Suivant cette tendance, une interface generique intelligente pour capteurs (Smart Sensor Interface - SSI), dediee aux capteurs de position avionique est proposee dans ce memoire. Le circuit integre SSI fera partie d'un reseau de capteurs AFDX ameliore et est compose de signaux d'excitation et de modules d'acquisition de donnees. Les efforts de conception sont concentres sur l'unite de generation de signaux d'excitation (Excitation Signal Generation - ESG) de la SSI. En tant que lien entre le reseau AFDX et les capteurs de deplacement, l'unite ESG doit generer des signaux sinusoidaux precis, d'une frequence allant de 1.5 kHz a 10 kHz. En respectant la programmation de l'interface, nous demontrerons qu'une architecture de generateur de signaux basee sur la memoire est la seule option qui reponde aux objectifs du design. Le design d'un convertisseur numerique-analogique (CNA) base sur le principe du sur-echantillonnage et faisant partie du chemin ESG est egalement presente dans ce travail. Ce CNA est le noyau d'un generateur de signaux sinusoidaux versatile concu pour le systeme SSI propose. Un taux d'echantillonnage eleve est utilise dans ce CNA, de facon a obtenir un rapport signal sur bruit (Signal to Noise Ratio - SNR) eleve. Une analyse de l'impact d'une implementation carree et non-carree de la matrice de sources de courant (Current Source Array - CSA) sur la performance de la sequence de commutation est presentee. Il sera demontre que la consideration de tels impacts conduit a la conception de CNA plus precis. Une sequence de commutation optimale pour la taille du CSA concu, sera introduite. Afin de reduire la taille des plots d'entrees et de sorties de la puce, un convertisseur de donnees serie a parallele haute-vitesse est inclu dans le CNA. Ainsi, les donnees d'entree peuvent etre envoyees de facon serielle a un registre a decalage et appliquees de facon interne au noyau du CNA.----------ABSTRACT Today, despite the astonishing advances in the field of Microelectronics, avionics systems are mostly employing older technologies to guarantee the level of reliability required by stringent safety standards of avionic systems. Toward the new generation of Integrated Modular Avionics (IMA) in More Electric Aircrafts (MEA), reliable and stable network architecture which employs modern integrated electronic modules must be designed and developed. In this trend, a generic Smart Sensor Interface (SSI) for avionics displacement sensors will be proposed in this Master thesis. The integrated SSI circuit will be part of an improved AFDX sensor network and consists of signal excitation and data acquisition paths. The design efforts of this Master thesis will focus on the Excitation Signal Generation (ESG) unit of the SSI. As a link between AFDX network and displacement sensors, the ESG unit should generate pure and accurate sine-waveform with variable frequency between 1.5 kHz and 10 kHz. Respecting the programmability of the interface, it will be shown that a memory-based signal generator architecture is the only choice which supports the design objectives. As part of the ESG path, the detailed design of a 10-bit interpolating digital to analog converter (DAC) will also be presented in this work. The DAC is the core of a versatile sine-waveform generator unit designed for avionics SSI. High-speed sample rate will be used in this segmented current steering DAC in order to achieve a high Signal to Noise Ratio (SNR). In the module level design of the DAC, the impact of square and non-square implementation of the current source array (CSA) on the performance of the switching sequence is introduced. It will be shown that considering such impacts will lead to the design of more accurate DACs. An optimum switching sequence for the designed CSA size will be designed and introduced. In order to reduce the I/O pads of the chip, high-speed serial to parallel converter will be included in the DAC. Thus the input data can be serially sent to the input shift register and internally applied to the DAC core. The DAC was fabricated on 1.2 × 1.2 mm2 chip fabricated using IBM 0.13µm CMOS technology, operating with a supply voltage of 1.2 V. Sourcing a sine wave current with a peak of 1023 µA, the proposed DAC is able to achieve a SNR better than 84 dB in the Nyquist bandwidth of DC to 20 kHz. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://publications.polymtl.ca/1127/1/2013_MasoodKarimian-Sichany.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
