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A High Speed 1 . 5-Bit Mismatch-Insensitive Multiplying Digital-to-Analog Converter
| Content Provider | Semantic Scholar |
|---|---|
| Author | Ashraf, Mohammadreza Yavari, Mohammad |
| Copyright Year | 2010 |
| Abstract | Abstract—A new method to reduce the mismatch between the capacitors of a 1.5 bit multiplying digital-to-analog converter (MDAC) structure is presented. The new structure employs two capacitors in series and operates in three phases. Compared to the conventional MDAC structure, the mismatch between the capacitors has a much smaller influence not only on the accuracy of the input signal but also on DAC voltage. Moreover, despite the addition of a phase, the speed of the proposed MDAC is higher than that of a conventional one. Circuit-level analysis and simulation results of the proposed architecture and the conventional structure are presented using a 90nm CMOS technology. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ele.aut.ac.ir/yavari/Conferences/Ashraf_ICECS_2010.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
