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Teaching Hardware Description Languages (Hdls)
| Content Provider | Semantic Scholar |
|---|---|
| Author | Degroat, Joanne Elizabeth |
| Copyright Year | 2005 |
| Abstract | This paper highlights the course content of “Theory and Design of Digital Computers, II” at The Ohio State University. The course has several topics of emphasis. The first and central topic covered in the course is the theory of Hardware Description Languages (HDLs), the simulation paradigm of VHDL, and modeling with HDLs at various levels of abstraction. The levels of abstraction starts at the gate level where the HDL description is one-to-one with the hardware modeled, i.e., there is a HDL modeling statement for each gate in the design. The level of abstraction continues to increase until at the end of the course the modeling is at the algorithmic level. The design projects used for each level of abstraction will be detailed. The other topics covered in the course deal with various aspects of computer architecture and digital systems. The detailed operation of the registers and an arithmetic/logic unit are explored. The operation of the control unit is also discussed, but in a quarter system there is not sufficient time to model it. Rather, the course moves on to advanced functional units, such as floating point units, and discussion of the IEEE Floating Point standard. A single precision floating point add/subtract unit is modeled. Thus, the course may emphasize the theory of and modeling with Hardware Description Languages, but the course also introduces the students to additional aspects of computer architecture and digital design. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://peer.asee.org/teaching-hardware-description-languages-hdls.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
