Design and Testing of a Radiation Hardened 13-bit 80 MS/s Pipeline ADC Implemented in a 90nm Standard CMOS Process

The first stage design of a SHA-less 12-bit 200-Ms/s pipeline ADC in 130-nm CMOS

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A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS

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A 10-bit 40 MS / s Pipelined ADC in a 0 . 13 μ m CMOS Process

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A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS

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High sampling rate 1 GS/s current mode pipeline ADC in 90 nm Si-CMOS process

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A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

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A 90-nm CMOS, 8-bit pipeline ADC with 60-MHz bandwidth and 125-MS/s or 250-MS/s sampling frequency

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Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

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