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DataScalar Architectures and the SPSD Execution Model
| Content Provider | Semantic Scholar |
|---|---|
| Author | Burger, Doug Kaxiras, Stefanos |
| Copyright Year | 2004 |
| Abstract | The increasing power of commodity microprocessors is forcing system designers to provide more complex and expensive memory hierarchies. A potentially cheaper and better-performing alternative in the long run is to integrate the processor and main memory on the same die or module. In this paper, we propose an architecture (DATASCALAR) and an execution model (SPSD) that permit efficient execution of uniprocessor programs across multiple integrated processor/memory modules. We then describe four features of this proposal that permit improved performance: ESP gains, memory prefetching, result communication, and hybrid parallel execution. Finally, we present examples and measurements, which give evidence that each feature will improve performance on future systems that have very expensive off-chip communication. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.cs.utexas.edu/ftp/dburger/papers/TR_1317.pdf |
| Alternate Webpage(s) | http://www.cs.wisc.edu/~kaxiras/papers/tr1317.pdf |
| Alternate Webpage(s) | http://cs.wisc.edu/~kaxiras/papers/tr1317.pdf |
| Alternate Webpage(s) | http://pages.cs.wisc.edu/~kaxiras/papers/tr1317.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
