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Ultra-Fast Automatic Placement for FPGAs
| Content Provider | Semantic Scholar |
|---|---|
| Author | Sankar, Y. Vidya |
| Copyright Year | 1999 |
| Abstract | Ultra-Fast Automatic Placement for FPGAs Master of Applied Science, 1999 Yaska Sankar Department of Electrical and Computer Engineering University of Toronto As Field-Programmable Gate Amy (FPGA) device capacities have grown, the computation time devoted to placement and routing of circuits has grown more dramatically than the available cornputer power. Thus, high-speed FPGA compilation tools are critical. This thesis presents an ultra-fast placement algorithm for FPGAs. It is based on a combination of multiple-level, bottom-up clustering and simulated annealing. It provides superior area results over a known high-quality placement tool on a set of large benchmark circuits, when both are restncted to short run times. It can generate a placement for a 100,000-gate circuit in 10 seconds on a 300 MHz Sun UltraSPARC. The high-quality tool, using a pure simulated annealing algorithm, generates a placement that is 24% better than our tool, but takes 524 seconds; it needs 50 seconds to achieve the same placement quality as Our tool. Furthemore, when operating in its fastest mode, our tool can provide an accurate estimate of the wirelength achievable with good quality placement. This can be used, in conjunction with a routing predictor, to very quickly determine the routability of a circuit on a given FPGA device. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.eecg.toronto.edu/~jayar/pubs/theses/Sankar/YaskaSankar.pdf |
| Alternate Webpage(s) | http://www.eecg.toronto.edu/~yaska/PS/thesis.1pg.2.ps.gz |
| Alternate Webpage(s) | https://tspace.library.utoronto.ca/bitstream/1807/12567/1/MQ45427.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
