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Design Optimization of Ultralow Capacitance InGaAs Waveguide Photodetector on III-V CMOS photonics platform
| Content Provider | Semantic Scholar |
|---|---|
| Author | Cheng, Pengyuan Takagi, Shinichi Takenaka, Mitsuru |
| Copyright Year | 2018 |
| Abstract | 【Introduction】To reduce the power consumption, the concept of receiver-less PDs was proposed, which requires ultra-low capacitance (<1fF). We have proposed III-V CMOS photonic platform which has uses a III-V on insulator (III-V-OI) wafer [1][2]. By using the III-V CMOS photonics platform, we have numerically investigated the ultra-low capacitance InGaAs PD [3] with a lateral PIN junction. In this study, we have conducted optimization in the dimensions of the PD to further improve the performance through maximizing the product of light-to-voltage conversion efficiency and 3-dB bandwidth. 【Device Structure】Figure 1 shows the a schematic of InGaAs rib waveguide PD with a lateral PIN junction on III-V-OI wafer, which is butt-coupled with an a-Si waveguide. Amorphous silicon waveguide deposited by PECVD enables flexible interconnection of III-V-OI active devices [4]. The rib height and length of waveguide PD are optimized to achieve highest product of light-to-voltage conversion efficiency and 3dB bandwidth or lowest power consumption. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://confit.atlas.jp/guide/event-img/jsap2018s/18p-B201-4/public/pdf?type=in |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
