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Basic Schemes to Exploit Loop-level Parallelism on the Cell Broadband Engine ⋆
| Content Provider | Semantic Scholar |
|---|---|
| Author | Abellán, José L. Fernandez, Juan Acacio, Manuel E. |
| Copyright Year | 2008 |
| Abstract | CMP architectures provide very high performance and are more energy-efficient than their contemporary single-core. However, programmers must be aware of a wide variety of communication and synchronization mechanisms in order to efficiently exploit thread-level parallelism (TLP). In this work, we present a workload scheduler for CMP architectures to achieve static and dynamic loop-level parallelism by loadbalancing work among all available cores, in order to minimizes idle time. As present and future work, we are extending our proposal to also tackle task-level parallelism. In particular, the CMP architecture under consideration in this work is a dual Cell-based Blade. This platform contains two Cell BEs providing a number of communication and synchronization mechanisms. In addition, it enables inter-Cell communications which further increases the complexity of making efficient load-balancing. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://para08.idi.ntnu.no/docs/submission_110.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |