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SystemC Manipulation Framework : from RTL VHDL to Optimized TLM SystemC
| Content Provider | Semantic Scholar |
|---|---|
| Author | Abrar, Syed Saif Tihhomirov, Valentin Jenihhin, Maksim Tallinn, Jaan Raik |
| Copyright Year | 2015 |
| Abstract | We propose a novel framework for SystemC manipulation based on the open-source hardware design and analysis environment zamiaCAD. The framework provides optimized VHDL-to-SystemC translation and subsequent abstraction to higher-level, including an Eclipse-based front-end. 1. Overview of zamiaCAD zamiaCAD [1] is a modular and extensible open source framework supporting multiple use-cases, like hardware design and debug, along with conversion and abstraction to SystemC, conforming to the IEEE Standard VHDL Language Reference Manual. Fig-1 shows the structure and applications of zamiaCAD. It can handle large industrial designs, such as a SoC made of 3500 Leon3MP-s, and provides all facilities through Eclipse-based GUI front-end. 2. VHDL to SystemC Translation IP design-houses have a large number of legacy IP cores described in VHDL whose reuse and integration into SystemC ecosystem is highly demanded. The zamiaCAD framework includes open-source methodology [2] to convert RTL VHDL IP cores to cycle-accurate SystemC designs. The SystemC output is emphasized to be human-readable and provides clear correspondence to the source VHDL code, thus allowing further manual code changes and debug. 3. SystemC Optimizations Various optimizations are performed on the SystemC code generated by zamiaCAD, such as: (1) Using native C++ datatypes for faster simulation, (2) Optimization of VHDL concurrent statements, (3) Abstraction for co-simulation. 4. SystemC Abstractions 1) Interface abstraction deals with the conversion of signallevel and cycle-accurate protocol to the standard TLM-2.0 protocol is SystemC. Our methodology can be used to abstract any arbitrary signal-level protocol to TLM-2.0, without affecting side-band signals like clock and interrupts. 2) Clock abstraction aims at removing the clock-signal, either partially or completely. Minimization of delta-cycles and events in a system-level model is the underlying idea. 3) Functional abstraction focus on abstracting the behavioral implementation of a module. Notion of SystemCbased Loose Modeling (SCLM) is introduced to functionally abstract a VHDL FSMD design, using goto statements. SCLM enables to neglect design model parts irrelevant for a particular abstraction. SCLM goto models can be easily transformed to a readable structured form (e.g. WHILE, FOR, etc). Table-I presents the experimental results for simulation speed-up provided by different stages of abstraction, for various benchmark designs. Un-optimized goto-code (GT) provides for a small speed-up. The optimized goto-implementation (GT_O) improves the simulation speed a little more. The last column demonstrates speed-up achieved by the untimed optimized goto (GT_O_U) model. Here the data dominated designs with less interruption of the computational phase by communication such as b07 and codec demonstrate a significant speedup up to 27.24 times. TABLE I. SIMULATION SPEED-UP BY ABSTRACTION Design RTL FSMD GT GT_O GT_O_U Gcd 1 1.25 1.71 2.65 b02 1 1.03 1.03 1.94 b07 1 1.09 1.10 12.08 Codec 1 1.35 1.42 27.24 |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.date-conference.com/files/file/date15/ubooth/7517.pdf |
| Alternate Webpage(s) | http://www.date-conference.com/files/file/date15/ubooth/7517.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
