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Performace modeling and optimization for on-chip interconnects in memory arrays
| Content Provider | Semantic Scholar |
|---|---|
| Author | Mohseni, Javaneh Pan, Chenyun Naeemi, Azad |
| Copyright Year | 2015 |
| Abstract | Performance modeling and optimization for on-chip interconnects in DRAM arrays are presented at various technology generations. Multiple interconnect design schemes and novel interconnect technology options are investigated to minimize the overall delay and energy-delay product. |
| Starting Page | 149 |
| Ending Page | 152 |
| Page Count | 4 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/EDAPS.2016.7874429 |
| Alternate Webpage(s) | https://smartech.gatech.edu/bitstream/handle/1853/60192/MOHSENI-DISSERTATION-2018.pdf?isAllowed=y&sequence=1 |
| Alternate Webpage(s) | https://doi.org/10.1109/EDAPS.2016.7874429 |
| Journal | 2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |